Today's SMAll editor will continue to introduce practICal skills in pcb design

1. Crosstalk free?

The changed signal (such as step signal) propagates from A to B along the transmission line, and the coupling signal will be generated on the transmission line C-D. Once the changed signal ends, that is, the signal recovers to the stable DC level, the coupling signal will disappear. Therefore, crosstalk only occurs in the process of signal jump, and the faster the signal changes along (conversion rate), the greater the crosstalk generated.

The coupLED electromagnetic field in space can be extracted as a collection of countless coupling capacitors and coupling inductors. The crosstalk signal generated by the coupling capacitor can be divided into forward crosstalk and reverse crosstalk Sc on the victim network, and the two signals have the same polarity; Crosstalk signals generated by coupling inductors are also divided into forward crosstalk and reverse crosstalk SLs, which have opposite polarities. The forward crosstalk and reverse crosstalk generated by coupling inductance and capacitance exist at the same time, and their sizes are almost equal. In this way, the forward crosstalk signals on the victim network cancel each other due to their opposite polarities, and the reverse crosstalk polarities are the same, which is superimposed and enhanced.

The modes of crosstalk analysis usually include default mode, tri state mode and worst case mode analysis.

The default mode is SIMilar to the way we actually test crosstalk, that is, the victim network driver is driven by the flip signal, the victim network driver maintains its initial state (high level or low level), and then calculates the crosstalk value. This method is more effective for one-way signal crosstalk analysis. Tri state mode means that the infringed network driver is driven by the flip signal, and the affected network's tri state terminal is set to the high resistance state to detect the crosstalk. This method is more effective for bidirectional or complex topology networks. The worst case analysis refers to keeping the drivers of the victim network in the initial state, and the simulator calculates the total crosstalk of all default victim networks to each victim network. This method generally only analyzes individual key networks, because there are too many combinations to be calculated and the simulation speed is relatively slow.

2. Is there any regulation on the copper area of the ground plane of the conduction band, that is, the microstrip line?

For microwave circuit design, the area of the ground plane has an effect on the parameters of the transmission line. The specific algorithm is relatively complex (please refer to related EESOFT materials of Angelan). For the transmission line simulation calculation of general PCB digital circuits, the area of the ground plane has no influence on the transmission line parameters, or the influence is ignored.

3. In the EMC test, it was found that the harmonic of the clock signal exceeded the standard seriously, and only the decoupling capacitor was connected to the power supply pin. What aspects should be paid attention to in PCB design to suppress electromagnetic radiation?

The three elements of EMC are radiation sources, transmission routes and victims. The transmission route is divided into space radiation transmission and cable transmission. So to suppress harmonics, first look at its propagation path. Decoupling of power supply is to solve the transmission of conduction mode. In addition, necessary matching and shielding are also required.

4. Why are some products designed with 4-layer boards double-sided and some products not?

There are several considerations for the role of flooring: 1, shielding; 2. Heat dissipation; 3. Reinforcement; PCB processing needs. So no matter how many layers of flooring, the first thing to see is its main reason. Here we mainly discuss the high-speed problem, so we mainly talk about the shielding effect. The surface paving is good for EMC, but the copper paving should be as complete as possible to avoid islands. In general, if there are many surface devices wired, it is difficult to ensure the integrity of the copper foil, which will also lead to the problem of cross segmentation of the inner signal. Therefore, it is recommended not to lay copper on surface devices or boards with many wires.

5. When a group of buses (address, data, command) drives multiple (up to 4, 5) devices (FLASH, SDRAM, other peripherals...), which method is used for PCB wiring?

The impact of routing topology on signal integrity is mainly reflected in the inconsistent arrival time of signals at each node, and the inconsistent arrival time of reflected signals at a node, which leads to deterioration of signal quality. Generally speaking, the star topology can make the signal transmission and reflection delay consistent by controlling several stubs of the same length to achieve better signal quality.

When using topology, consider the signal topology node, actual working principle and wiring difficulty. Different buffers have different reflection effects on signals, so the star topology can not solve the above delay of data address bus connection to flash and sdram, and thus can not ensure the signal quality; On the other hand, high-speed signals generally communicate between dsp and sdram, and the flash loading speed is not high, so during high-speed simulation, it is only necessary to ensure the waveform at the node where the actual high-speed signal works effectively, without paying attention to the waveform at the flash; Compared with daisy chain topology, star topology is more difficult to route, especially when a large number of data address signals adopt star topology. The attached figure shows the simulation waveform at 150MHz when using Hyperlynx simulation data signal to connect with DDR - DSP - FLASH topology and DDR - FLASH - DSP. It can be seen that in the second case, the signal quality at DSP is better, while the waveform at FLASH is worse, while the actual working signal is the waveform at DSP and DDR.

6. For PCB with frequency above 30M, whether automatic wiring or manual wiring is used for PCB wiring; Are the software functions of cabling the same?

Whether the high-speed signal is based on the rising edge of the signal rather than the absolute frequency or speed. Automatic or manual routing depends on the support of the software routing function. Some manual routing may be better than automatic routing, but some routing, such as checking distribution lines and bus delay compensation routing, will be much more effective and efficient than manual routing. Generally, PCB substrate is mainly composed of resin and glass fiber cloth. Due to different proportions, the dielectric constant and thickness are different. Generally, the higher the resin content, the thinner the dielectric constant. Consult the PCB manufacturer for specific parameters. In addition, with the emergence of new processes, there are also some PCB boards made of special materials for the needs of ultra thick backplanes or low loss RF boards.

7. In PCB design, ground wire is usually divided into protective ground and signal ground; The power supply ground is divided into digital ground and analog ground. Why should the ground wire be divided?

The purpose of land division is mainly for EMC's consideration, and it is worried that the power supply of digital part and the noise on the ground will interfere with other signals, especially analog signals through the transmission path. As for the division of signal and protective ground, the consideration of ESD static discharge in EMC is similar to the role of lightning rod grounding in our life. No matter how divided, there is only one land in the end. It's just that the way of noise EMIssion is different.

8. Is it necessary to add ground wire shielding on both sides when laying clocks?

Whether to add a shielded ground wire depends on the crosstalk/EMI condition on the board. If the shielded ground wire is not handled properly, it may make the situation worse.

9. What are the corresponding countermeasures when laying clock lines of different frequencies?

For the wiring of clock wire, it is better to conduct signal integrity analysis, formulate corresponding wiring rules, and conduct wiring according to these rules.

10. When the PCB single layer board is manually wired, is it placed on the top layer or the bottom layer?

If it is a top layer amplifier, the bottom layer wiring.

This article mainly introduces 10 practical PCB wiring skills in the design of pcb circuit board